Chapter 7 · Book pp. 113–118

Applied Digital Circuits 1: the Latch IC

เรียน-เล่น-รู้ กับวงจรดิจิทัลขั้นประยุกต์ 1 - ไอซีวงจรแลตช์

With the basics from Chapter 6, it is time to apply digital ICs. This chapter starts with the latch. Chapter 8 then tries counter ICs to drive LEDs, Chapter 9 a decoder for a 7-segment display, and Chapter 10 builds adders — from a 1-bit adder made of gates up to a 4-bit adder IC.

7.1 Starting with the buffer วงจรบัฟเฟอร์

“Latch” means a bolt, like the one on a door: once it is shut, nobody gets in. A latch circuit is the same. Data passes through it, but once the latch signal is given, no new data gets in. It keeps the last data that came in until it is opened again by a new latch signal.

Latch ICs grew out of the tri-state buffer. An ordinary buffer’s output follows its input straight away and is always either high or low. When you need the output to float, you use a tri-state buffer.

**Fig 7-1**Tri-state buffer symbols and truth tables: with an active-low enable (top) and an active-high enable (bottom). Z = high impedance, or a “floating” output

The input that controls whether the signal reaches the output is the output enable (OE), which can be active on “0” or on “1”. Without the right enable signal, nothing reaches the output. That makes tri-state buffers useful for selecting signals:

**Fig 7-2**Tri-state buffers selecting signals, depending on the output enable (OE). Z means high impedance

Next: how a latch works →

7.2 How a latch works หลักการทำงานของวงจรแลตช์

A latch is like a tri-state buffer, except that it can hold its output even when the input changes. Fig 7-3 compares a buffer with a latch, sending the data 1101 one bit at a time.

**Fig 7-3**A buffer compared with a latch: the buffer’s output follows each input at once; with the latch signal at “1”, the latch stops new data and keeps its old output; with it at “0”, the output follows the input

Fig 7-4 is the logic diagram of a 1-bit data latch. Data on D reaches the output Q when:

logic “1” is given to LE (latch enable), so the data on D passes into the latch, and
logic “0” is given to OE (output enable), which turns on the tri-state output buffer so the data reaches Q.

Q then stays the same until new data arrives on D and the right control signals are given to LE and OE.

**Fig 7-4**Logic diagram of a 1-bit data latch: OE, LE, D, the internal latch and the output buffer to Q

7.3 The latch IC แนะนำไอซีวงจรแลตช์

The latch IC used here is the 74HC75. It has two 2-bit latches that together make a 4-bit latch:

Latch set 1: inputs 1D0, 1D1, outputs 1Q0, 1Q1, enable 1E (active on “0”).
Latch set 2: inputs 2D0, 2D1, outputs 2Q0, 2Q1, enable 2E (active on “0”).

**Fig 7-5**Pinout and truth tables of the 74HC75 latch IC. Q0 means the logic state from before (held)

Next: testing the 74HC75 →

7.4 Testing the 74HC75 ทดลองใช้งานไอซีแลตช์ 74HC75

A 4-way DIP switch SW1 sets the input data. The inputs have pull-ups: OFF = “1”, ON = “0”.
Press SW2 (LATCH) and the 4-bit data goes through to the Q outputs and the LEDs.
Release SW2 and the outputs keep that data, whatever you do to SW1, until you press SW2 again.

**Fig 7-6**Test circuit for the 74HC75 4-bit latch: SW1 data switches with 10k pull-ups (ON = 0, OFF = 1), SW2 LATCH, and four LEDs on Q0–Q3

🛠️ Lab 7.1 · Latch 4 bits of data

Build Fig 7-7 in Tinkercad. Set the 4 DIP switches to choose the data, then press SW2 and watch the LEDs. Compare with Fig 7-8.
Build it with real parts (Fig 7-9) and repeat step 1.

**Fig 7-7**Testing the 74HC75 on Tinkercad by simulation. SW1 DATA: ON = “0”, OFF = “1”

**Fig 7-8**Example results from the 74HC75 4-bit latch: in each of 8 tries, the LEDs keep the old data until SW2 is pressed, then show the new data

Try	Data D0–D3	LEDs Q0–Q3 before pressing SW2	After pressing SW2
1	1111	0000	1111
2	0111	1111	0111
3	0011	0111	0011
4	0001	0011	0001
5	1000	0001	1000
6	1100	1000	1100
7	0100	1100	0100
8	0110	0100	0110

Fig 7-8 written out: 1 = LED on. Each row’s “before” is the previous row’s result.

**Fig 7-9**Testing the 74HC75 with real parts on a breadboard. Scan the QR code for the demo video

Next: review →

Buffer or latch?

	Tri-state buffer	Latch (74HC75)
Output follows input?	Yes, at once (when enabled)	Only while the latch enable is active
Holds data?	No	Yes — the last data, until the next latch
Third state	Z (high impedance)	—
Typical use	Choosing which signal drives a shared wire	Remembering data for a display or output

🛠️ Activity · Predict, then latch

Before each press of SW2, write down which LEDs you expect to light. Remember ON = “0”.
Set data 1010, press SW2, then change the switches to 0101 without pressing SW2. What do the LEDs show? Why?
Which two pins of the 74HC75 would you use to latch only bits 0 and 1? Try it.

Check yourself

Chapter 7 has a worked test but no exercises, so these questions are my own, based on its pages.

1. What does the “Z” state of a tri-state buffer mean?

2. A buffer with an active-low enable (OE with a bar) has OE = 0 and A = 1. What is Y?

3. Why can two tri-state buffers share one output wire (Fig 7-2)?

4. What is the key difference between a buffer and a latch?

5. In the 1-bit latch (Fig 7-4), what lets the data on D through to Q?

6. How many latches does a 74HC75 contain?

7. In the test circuit, a DIP switch is ON. What does that data input read?

8. You change the DIP switches but do not press SW2. What do the LEDs do?