Cambridge AS & A Level · Part 3 · Chapter 18
Hardware and Virtual Machines
How a control unit is built, why RISC processors are designed for pipelining, the four ways to organise instruction and data streams, and how software can pretend to be a whole computer. Every figure, question and exam question from the chapter is here, with labs to try each idea.
Guru Jazzy🎯 Learning objectives
By the end of this chapter you should be able to:
- show understanding of Reduced Instruction Set Computers (RISC) and Complex Instruction Set Computers (CISC) processors
- show understanding of the importance and use of pipelining and registers in RISC processors
- show awareness of the four basic computer architectures: SISD, SIMD, MISD, MIMD
- show understanding of the characteristics of massively parallel computers
- show understanding of the concept of a virtual machine
🧠 18.01 The control unit Book p.341
While a program runs, the CPU receives a stream of machine-code instructions. The control unit (CU) inside the CPU is responsible for making sure each machine instruction is handled correctly. There are two ways to design a control unit:
The control unit is built as a logic circuit. The machine-code instructions are handled directly by hardware.
- Fast: no extra step to look anything up.
- Hard to design for a large, complicated instruction set.
- Fixed: changing the instruction set means changing the circuit.
The control unit contains a ROM that stores the microinstructions (microcode) for each machine instruction. This stored microcode is often called firmware.
- Each machine instruction runs as a short sequence of microinstructions.
- Easier to handle many complex instructions.
- Slower than hard-wiring, because of the extra level.
🎮 Hard-wired or microprogrammed?
Read each statement and decide which kind of control unit it describes.
⚙️ 18.02 CISC and RISC processors Book pp.341–342
A processor has an architecture, meaning its physical construction. It also has an instruction set architecture, which is concerned with:
- The instruction set
- The instruction format
- The addressing modes
- the registers accessible by instructions.
The choice of instruction set is the main factor that distinguishes one instruction set architecture from another.
In the early days of computing, a big factor in choosing an instruction set was making it easier to write a compiler for a high-level language. The term did not exist then, but we would now call this a Complex Instruction Set Computer (CISC). In the late 1970s people began to argue that a Reduced Instruction Set Computer (RISC) would be a better approach.
Table 18.01 Comparison of RISC with CISC
| RISC | CISC |
|---|---|
| Fewer instructions | More instructions |
| Simpler instructions | More complex instructions |
| Small number of instruction formats | Many instruction formats |
| Single-cycle instructions whenever possible | Multi-cycle instructions |
| Fixed-length instructions | Variable-length instructions |
| Only load and store instructions to address memory | Many types of instructions to address memory |
| Fewer addressing modes | More addressing modes |
| Multiple register sets | Fewer registers |
| Hard-wired control unit | Microprogrammed control unit |
| Pipelining easier | Pipelining more difficult |
Points to note
- For RISC, "reduced" means more than just the number of instructions. Cutting the number of instructions is not the main reason for using RISC.
- The key feature of RISC is the reduced complexity of each instruction.
- A typical CISC architecture has many specialised instructions, designed to match the needs of a high-level programming language.
- Those specialised instructions need several memory accesses, which are very slow compared with register accesses.
- Because RISC instructions are simple, data can be loaded into registers and worked on there, with no memory access apart from the first load and, possibly, a final store.
- Simple RISC instructions make it easier to hard-wire the control unit.
- Many CISC instructions are complex, which makes hard-wiring much harder, so microprogramming is the norm.
Can you find out whether the processors in any systems you are using are described as RISC or CISC?
Some starting points
- Most phones and tablets, and Apple's M-series Macs, use ARM processors: a RISC design.
- Most Windows laptops and desktops use Intel or AMD x86-64 processors: a CISC instruction set. Inside, modern x86 chips translate the complex instructions into simpler RISC-like micro-operations before they run them.
- The Raspberry Pi uses an ARM (RISC) chip. Arduino boards use AVR microcontrollers, which are also RISC.
🎮 RISC or CISC?
Each statement comes from Table 18.01 or the notes. Which processor type does it describe?
🚰 Pipelining Book pp.342–344
One of the main reasons for creating RISC processors was the chance they give for efficient pipelining. Pipelining is a form of parallelism applied specifically to instruction execution. Other forms of parallelism are covered in Section 18.03.
The idea is that the fetch–decode–execute cycle (Chapter 5, Section 5.06) can be split into a number of stages. One possibility is a five-stage model:
- Instruction fetch (IF)
- Instruction decode (ID)
- Operand fetch (OF)
- Instruction execute (IE)
- Result write back (WB)
To pipeline these five stages, the processor must have five independent units, each handling one stage. That is why a RISC processor needs many register sets: each processor unit must have its own set of registers.
Figure 18.01 writes 1.1, 1.2 and so on for "instruction 1, stage 1", "instruction 1, stage 2". At first only stage 1 of instruction 1 is in the pipeline. By clock cycle 6, instruction 1 has left the pipeline, the last stage of instruction 2 is being handled, and instruction 6 has just entered.
Once it is running, the pipeline handles five stages of five different instructions at once, and one instruction finishes every clock cycle. Without the pipeline, processing would take five times as long.
🧪 Pipeline lab
Choose how many instructions to run and press Step to move one clock cycle at a time. Try the hazard options to see the problem from the Discussion Point below, and one way to fix it.
Pipelining and interrupts
Chapter 5 (Section 5.08) described a processor that handles instructions one after another and checks for an interrupt after each instruction has executed. That works for a CISC processor, and for a RISC processor without pipelining, which is unlikely. In a pipelined system there will be five instructions in the pipeline when an interrupt arrives. There are two options:
- Flush the pipeline: erase the contents of the pipeline for the latest four instructions to have entered, then apply the normal interrupt-handling routine to the remaining (oldest) instruction. The erased instructions are fetched again after the interrupt.
- Give each unit its own program counter: build the individual processor units with their own program counter registers, so the current data for every instruction in the pipeline can be stored while the interrupt is handled.
Consider the two consecutive instructions ADD R1, R2, R3 and ADD R5, R1, R4. These are typical three-register instructions favoured by RISC. The first adds R2 and R3 and stores the result in R1. The second is similar but uses the value stored in R1. In a pipeline, the second instruction will be reading R1 before the first instruction has put the value there. How could this potential problem be overcome?
Ideas to discuss
- Stall (insert bubbles): hold the second instruction back until the first has written R1. Simple, but it wastes clock cycles. Try "stall" in the lab above.
- Operand forwarding (bypassing): pass the ALU result straight from the execute unit to the next instruction's execute stage, without waiting for write-back. Try "forwarding" in the lab: no cycles are lost.
- Reorder instructions: the compiler puts an independent instruction between the two, so useful work fills the gap.
- Insert a NOP (no-operation instruction) as a simple software fix.
This kind of clash is called a data hazard. The name goes beyond the syllabus, but the ideas are good evidence of understanding.
🎲 Pipeline timing practice
Fresh numbers each time. Assume no hazards: every stage takes one clock cycle.
🔀 18.03 The basic computer architectures Book pp.344–346
A well-established way to describe computer architectures is to count the number of instruction streams and the number of data streams. This gives four types.
| Single data stream | Multiple data streams | |
|---|---|---|
| Single instruction stream | SISD: early computers, first microprocessors | SIMD: array / vector processors, multi-core |
| Multiple instruction streams | MISD: no real single architecture; fault-tolerant idea | MIMD: multiprocessors, massively parallel computers |
Single Instruction Stream Single Data Stream (SISD)
SISD is the typical arrangement in early computers, and the earliest microprocessors used it too. Processing is purely sequential, with no parallelism. Figure 18.02 shows how the elements of an array are processed with SISD: the same instruction is used repeatedly to multiply each element by two.
Single Instruction Stream Multiple Data Stream (SIMD)
SIMD can be thought of as parallelism applied to the data stream. Figure 18.03 shows the difference when the same array is processed: one instruction doubles all four elements at once.
🧪 SISD vs SIMD race
Both processors must double every element of the same array. Press Tick to give each one clock cycle.
SISD: one element per instruction
0 instructions
SIMD: one instruction, four PUs
0 instructions
SIMD is usually drawn as in Figure 18.04: four data streams enter four separate components, which are all supplied with the same instruction at the same time. The components are labelled PU (Processing Unit), or sometimes PE (Processing Element). Whatever the name, the components are arithmetic logic units. The different names exist because there are different ways to build this architecture.
Two ways to build SIMD:
- Array or vector processors: these might have a parallel set of registers, one for each data stream. Or there could be one large register, perhaps 64 or 128 bits, holding four data values at the same time. The parallelism is built into just one processor.
- Multi-core processor: four individual processors work in parallel. Each processor is likely to have its own dedicated cache memory to supply its data stream.
Multiple Instruction Stream Single Data Stream (MISD)
MISD does not appear in any individual computer architecture design. One place it could be used is a fault-tolerant system: the same data stream is fed into two or more processors, and the output is accepted only if all the processors produce the same output.
Multiple Instruction Stream Multiple Data Stream (MIMD)
MIMD is like the SIMD diagram in Figure 18.04, with more than one processing unit receiving parallel data streams. The difference is that each processing unit does not execute the same instruction. The data streams can come from a suitably partitioned single memory, and each processing unit might have its own dedicated cache memory.
Massively parallel computer systems
MIMD can be implemented in multicomputer systems known as massively parallel computers. Large organisations use them for computations involving highly complex mathematical processing. They are the latest type of "supercomputer".
- Instead of a bus structure supporting multiple processors, there is a network infrastructure supporting multiple computer units.
- The programs running on the different computers communicate by passing messages over the network.
- Another kind of multicomputer system is cluster computing, which uses PCs (sometimes called a "server farm").
- Whatever the technology, these systems have an extremely large number of individual processors working in parallel.
The IBM Sequoia and a Beowulf cluster are different examples of cluster computing. You might want to research some details of their computing power.
Some starting points
- IBM Sequoia (Lawrence Livermore National Laboratory, 2012) was a Blue Gene/Q system with about 1.6 million processor cores. It reached roughly 16–20 petaFLOPS and was the world's fastest computer in June 2012.
- A Beowulf cluster is built from ordinary, cheap PCs, often running Linux, joined by a local network and using message-passing libraries such as MPI. Schools sometimes build small ones from Raspberry Pis.
- Look up the current TOP500 list to compare today's fastest systems.
🎮 Which architecture?
Classify each system or description.
🖥️ 18.04 Virtual machines Book pp.346–347
A virtual machine is software, not hardware. The most usual type is the system virtual machine: software that emulates the hardware of a real computer system.
Without a virtual machine, an application program needs an operating system to support it so that it can run on the hardware. With a virtual machine, a process interacts directly with a software interface provided by an operating system. Figure 18.05 shows the logical structure of a system virtual machine.
🧪 Explore the layers
Tap any layer of this rebuilt Figure 18.05 to see what it does.
The "Native app" box is my addition, showing point 3 below: programs can also run directly on the host OS at the same time.
Points to note about Figure 18.05:
- The application programs are installed with the help of a guest OS. The guest OS supports the running application by interacting with the virtual machine as though it were the hardware that the guest OS would normally run on.
- The virtual-machine implementation software can be thought of as a utility program. When it runs, it is supported by the particular host OS, which is specific to the host hardware.
- Other application programs can run at the same time directly on the host hardware, under the control of the host OS.
- More than one different operating system can be made available on one computer system.
- Valuable when an organisation has legacy systems and wants to keep using the old software without keeping the old hardware.
- Large mainframe companies can offer server consolidation: the same OS made available many times, so different companies each get their own virtual machine running as a server.
- The time and effort needed for implementation.
- The implementation will not offer the same level of performance as a normal system.
Are there other advantages or disadvantages in using a system virtual machine?
Ideas to discuss
- + Isolation and security: a crash or virus in one guest does not affect the others or the host; good for testing suspicious software.
- + Safe testing: new software, updates or a new OS can be tried on a VM without risking the live system.
- + Snapshots and backups: a whole machine can be saved, copied, restored or moved to other hardware.
- + Better use of hardware: several lightly used servers can share one physical machine, saving cost, space and energy.
- − Shared resources: guests compete for the same CPU, memory and disk, so one busy VM can slow the others.
- − Single point of failure: if the host hardware fails, every VM on it goes down.
- − Hardware access: some devices (special graphics cards, dongles) may not work fully through the emulated hardware; licences may be needed for every guest OS.
Process virtual machines
The Java virtual machine from Chapter 8 (Section 8.05) is an example of a process virtual machine, which is based on a different idea. A process virtual machine provides a platform-independent programming environment, so a program runs in the same way on any platform. It is specific software that only supports running a Java program. A system virtual machine supports any application.
| System virtual machine | Process virtual machine (e.g. JVM) | |
|---|---|---|
| Emulates | A whole computer's hardware | A platform for one kind of program |
| Runs | A complete guest OS plus any applications | One program (e.g. Java byte code) at a time |
| Main purpose | Several OSs on one machine, legacy systems, server consolidation | Platform independence: write once, run anywhere |
A checklist
- System virtual machine: software emulating a whole computer (this chapter).
- Process virtual machine / JVM: software that runs byte code on any platform (Chapter 8).
- Virtual memory: using disk space to extend apparent main memory, with paging (Chapter 20).
- Virtual circuit: a logical path set up through a network before data is sent (Chapter 17).
📌 Summary
- A control unit can be hard-wired or microprogrammed.
- RISC (Reduced Instruction Set Computer) processors have a number of advantages compared with CISC (Complex Instruction Set Computer) processors.
- Pipelining is one of the reasons for choosing a RISC architecture.
- Parallelism can be based at the instruction level, the processor level or the computer level.
- A system virtual machine is software emulating hardware.
- The Java Virtual Machine is an example of a process virtual machine.
🃏 Key-term flashcards
Tap a card to flip it.
✅ Quick quiz
🏷️ Practice: label the virtual machine diagram (Exam question 2a)
📝 Exam-style questions
Write your answer first, then open the model answer. These are my mark-scheme-style points, not official mark schemes.
(i) Reduced Instruction Set Computer.
(ii) Any four:
- Fewer, simpler instructions.
- Few instruction formats; fixed-length instructions.
- Single-cycle instructions wherever possible.
- Only load and store instructions address memory.
- Fewer addressing modes.
- Multiple register sets / many general-purpose registers.
- Hard-wired control unit.
- Designed to make pipelining easy.
(i) The control unit is hard-wired (1). It is built as a logic circuit (1), so each machine-code instruction is handled directly by hardware (1), not by running stored microcode.
(ii) Microprogramming (1). The control unit needs a ROM to hold the microinstructions / microcode (firmware) (1).
(a) A: guest operating system · B: virtual machine · C: virtual-machine implementation software (hypervisor / virtual machine monitor) · D: host operating system.
(b) Two marks each:
- A guest OS: the operating system that Application program 1 was written for. It supports the application and interacts with the virtual machine as if it were real hardware.
- B virtual machine: software that emulates the hardware of a real computer system, providing the interface the guest OS expects.
- C VM implementation software: a utility that creates and manages the virtual machine(s), translating their requests into requests to the host OS.
- D host OS: the operating system specific to the real hardware. It controls the hardware and runs the VM software and any native applications.
(c) Application 2 runs directly under the host OS (1): it was written for the host OS, so it does not need a guest OS or a virtual machine (1).
(i) Instruction-level parallelism; processor-level parallelism (e.g. SIMD / multi-core); computer-level parallelism (e.g. massively parallel / cluster computing). Accept SIMD, MISD, MIMD as the types.
(ii) Instruction-level parallelism.
(iii) Draw a grid like Figure 18.01: stages down the side, clock cycles across the top. Points:
- The fetch–execute cycle is split into stages, e.g. IF, ID, OF, IE, WB.
- Each stage is handled by a separate processor unit with its own registers.
- Each clock cycle, every instruction moves on one stage and a new instruction enters.
- So several instructions are being processed at once, each at a different stage.
- Once the pipeline is full, one instruction completes every clock cycle.
- When an interrupt arrives there are several instructions (five) part-way through the pipeline, not one finished instruction (1).
- Option 1: flush the pipeline, erasing the latest four instructions, handle the interrupt after the oldest instruction finishes, then re-fetch the erased ones (1).
- Option 2: give each processor unit its own program counter, so the state of every instruction in the pipeline can be saved while the interrupt is handled (1).
- Makes extensive use of general purpose registers → RISC
- Many addressing modes are available → CISC
- Has a simplified set of instructions → RISC
(i)
| Stage | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
|---|---|---|---|---|---|---|---|---|---|
| Fetch instruction | A | B | C | ||||||
| Decode instruction | A | B | C | ||||||
| Execute instruction | A | B | C | ||||||
| Access operand in memory | A | B | C | ||||||
| Write result to register | A | B | C |
(ii) Without pipelining: 3 instructions × 5 stages = 15 clock cycles (1). With pipelining: 5 + (3 − 1) = 7 clock cycles (1). Saving = 15 − 7 = 8 clock cycles (1).
Cambridge International AS & A Level Computer Science 9608, Paper 31 Q4, November 2015
(i) Any two:
- Creates / emulates the virtual hardware that each guest OS runs on.
- Allocates the real resources (processor time, memory, storage) between the guest operating systems.
- Translates / passes on each guest OS's hardware requests to the host OS, and returns the results.
- Keeps the virtual machines isolated from each other, so one cannot interfere with another.
(ii) The host OS runs directly on (controls) the real hardware (1). A guest OS runs on a virtual machine, under the control of the VM software, and believes it is controlling real hardware (1).
(i) Any two, each described (2 marks each):
- Testing: install candidate new OSs, and the new web server software, as guests on a VM, and test them without touching the live server, so the service is not disrupted.
- Running the old system: keep the existing OS and web server running as a guest on a VM on new hardware, so the old (legacy) software can carry on while the change is prepared.
- Running old and new side by side: run the old and new set-ups at once and switch over when the new one is proven, giving a smooth changeover.
(ii) A VM does not give the same performance as the real system (1). So testing on it cannot show how the new set-up will cope with the real load of many simultaneous requests (1).
Cambridge International AS & A Level Computer Science 9608, Paper 31 Q3, June 2016
Guru Jazzy · Cambridge AS & A Level Computer Science · Chapter 18 Hardware and Virtual Machines · Figures from the Cambridge coursebook (Langfield & Duddell)