CS · Chapter 5

Cambridge AS & A Level · Part 1 · Chapter 5

Processor Fundamentals

What is inside the CPU, how it talks to memory over the buses, and the cycle it repeats billions of times a second. Every figure, question and exam question from the chapter is here, with labs to step through each idea.

Guru Jazzy

Chapter 5 opener: tracks and chips on a motherboard

🎯 Learning objectives

By the end of this chapter you should be able to:

explain the basic von Neumann model and the stored program concept
explain the purpose of registers, and the difference between general-purpose and special-purpose registers
explain the roles of the ALU, the control unit, the system clock and the immediate access store (IAS)
explain how data moves between components on the address, data and control buses
explain how different factors affect system performance
explain how ports connect peripheral devices
describe the stages of the fetch–execute (F–E) cycle
Explain the purpose of interrupts

🏛️ 5.01 The von Neumann model

John von Neumann was the first to publish a description of how a computer system should be organised. His model has five basic features:

There is one processor: the central processing unit (CPU).
The processor has direct access to memory.
Memory holds a stored program, and the data that program needs. The program can be swapped for another at any time.
The stored program is made of individual instructions.
The processor carries out the instructions one after another (sequentially).

Stored program concept: program instructions and data sit together in main memory, and the processor fetches and executes the instructions from there one at a time.

🧩 5.02 CPU architecture Figure 5.01

To see how the model works in real hardware, start with the smallest CPU that could do the job.

**Figure 5.01**A simple CPU: the control unit, ALU and registers (PC, MAR, MDR, CIR and others) inside the processor boundary, linked to the address, data and control buses

The dotted line is the edge of the processor. Arrows show which way data can flow. "Data" here is used loosely: along some arrows it is really an address or an instruction, and along others a value.

The two active components

Arithmetic and logic unit (ALU): does the arithmetic and logic processing that the program's instructions need.

Control unit (CU): controls the flow of data through the processor and the whole system, and makes sure instructions are handled correctly.

The control unit relies on a clock to keep everything in step. Strictly there are two:

Internal clock: controls the cycles of activity inside the processor.

System clock: controls the cycles of activity outside the processor.

The frequency of the clock is the clock speed. It sets the shortest time that can separate one activity from the next.

Registers

The rest of the CPU is registers: small storage locations right next to the ALU, so they can be reached very quickly. Each holds only 16, 32 or 64 bits. A register is either general purpose or special purpose.

Accumulator (ACC): a general-purpose register that holds a value before and after an instruction is executed by the ALU. In this chapter and Chapter 6, the processor has just this one general-purpose register.

The "Other registers" box in Figure 5.01 stands for the accumulator plus the special-purpose registers not drawn on their own. The special-purpose registers of our simple CPU:

Register	Short name	What it holds
Current instruction register	CIR	the instruction being decoded and executed right now
Index register	IX	a value used only for indexed addressing
Memory address register	MAR	the address of the memory location (or I/O component) about to be read from or written to
Memory data register (memory buffer register)	MDR (MBR)	data just read from memory, or about to be written to it
Program counter	PC	the address of the next instruction to be fetched
Status register	SR	individual bits (flags) that are set or cleared, each checked on its own

Three things to remember

The MDR acts as a buffer, because transfers inside the processor are much faster than transfers outside it.
Some sources write the index register as "IR", and others use "IR" for the current instruction register. In this book the index register is always IX and the current instruction register is always CIR.
PC means "program counter" only in register transfer notation. Anywhere else, a PC is a personal computer.

Every special-purpose register holds a single value, except the status register. There, each bit is a separate logical flag, set to 1 when a condition is detected: for example the carry, negative and overflow flags. Chapter 6.07 uses the accumulator and status register in real programs.

🔬 Lab: set the status flags

The ALU adds two 8-bit numbers and leaves the result in the accumulator. Treat the bytes as two's complement for N and V. Toggle each flag that should be set to 1, then check.

C = carry out of bit 7 · N = result's top bit is 1 · V = two numbers of the same sign gave a result of the other sign · Z = result is zero

🎮 Which register?

🚌 5.03 The system bus Figure 5.02

A bus is a set of parallel wires, each carrying one bit. A bus is not a storage device: it holds nothing. It is the route data takes from one component to another.

The CPU has buses inside it too, but this section is about the system bus, which joins the CPU to memory and to the I/O system. It has three parts. Each connects to one CPU component (Figure 5.01):

The address bus connects to the MAR
The data bus connects to the MDR
the control bus connects to the control unit

**Figure 5.02**The system bus: the control, address and data buses connecting the CPU, memory and I/O

Bus	Carries	Direction	Notes
Address	an address, put on the bus from the MAR when the control unit says so	one-way: CPU → memory controller or I/O controller	It can never carry an address back to the CPU.
Data	data, which may be an instruction, an address or a value	two-way	Between CPU and memory, or to/from I/O. Some systems send input via the CPU first; others allow direct transfer to memory.
Control	control and timing signals	two-way: to and from the control unit	Typically only about 8 wires. Timing signals, set by the system clock, make sure one component sends exactly when another reads.

Address bus: carries an address, either to the memory controller to pick a location to read or write, or to the I/O system to pick the source or destination of data.

Data bus: carries data from the processor to memory or an output device, or from memory or an input device.

🎮 Which bus?

⚡ 5.04 What makes a system fast?

Clock speed

One clock cycle is the shortest time any action can take, so clock speed matters a great deal. But nothing outside the processor can keep up with it. The memory the processor can address directly, the immediate access store (IAS), sends and receives data far more slowly than the processor works.

Cores and cache

Modern CPU chips are multi-core: each core is a separate processor, and more cores means better performance.
Cache memory (Chapter 3.01 and 3.03) is the fastest part of the IAS. A bigger, faster cache improves performance, and putting all or part of it on the CPU chip gives the fastest access.

Word length

Word: a small number of bytes that the computer system handles as a single unit.

Typical word lengths are 16, 32 or 64 bits (2, 4 or 8 bytes). The word length shapes the design: registers are usually one word wide, and bus widths are chosen with it in mind.

Bus width

Address bus: its width is the number of bits in an address. A 16-bit bus can address 2¹⁶ = 65 536 locations, far too few for a modern computer. Even 32 bits gives only about four billion. Larger memories need special techniques, and those cost performance.
Data bus: ideally as wide as the word, so a word moves in one transfer. If it is only half the word length, each word needs two transfers, which slows the system down.

🔬 Lab: bus width calculator

Address bus 16 bits

Word bits Data bus bits

🎮 Drill

🔬 Lab: clock speed → time per cycle

Time for one cycle = 1 ÷ frequency. 1 GHz = 10⁹ cycles per second, so 1 GHz gives 1 ns per cycle.

Clock 1.7 GHz

Extension Question 5.01 A laptop advert says: 4 GB, 1 TB, 1.7 GHz. (a) Which three components do these describe? (b) Work out the shortest time that could separate two successive activities on this system.

Show an answer

(a) 4 GB is the size of main memory (RAM); 1 TB is the capacity of secondary storage (hard disk or SSD); 1.7 GHz is the processor's clock speed.
(b) One clock cycle: 1 ÷ (1.7 × 10⁹) s ≈ 5.9 × 10⁻¹⁰ s ≈ 0.59 ns.

Extension Question 5.02 Can you find out the bus widths used in the computer you are using?

A browser cannot see the buses, but it can sometimes report whether your system is 32- or 64-bit, which usually matches the word length and the register size. For full details, look up your processor model online.

🔌 5.05 I/O ports

Figure 5.02 makes it look as if the CPU, memory and I/O devices all use the buses in the same way. They do not. Each I/O device connects to an interface called a port, and each port connects to an I/O (device) controller, which handles the conversation between the CPU and that device.

Internal port: for an I/O device that is built into the computer.

External port: lets the user plug in a peripheral device.

The Universal Serial Bus (USB)

Connecting a peripheral to an early PC needed technical skill. The plug-and-play idea was that anyone could connect a device and use it at once, and the USB standard finally made that real. Today every new peripheral is expected to use USB; an alternative, FireWire, is much less common.

It supports a hierarchy of connections, with the computer at the root.
The computer can handle up to 127 attached devices.
Devices can be plugged in while the computer is on, and are configured automatically.
The standard keeps evolving; the book describes USB 3.2 as the latest version.

Tip: USB is a bus. A USB drive stores data; it plugs into a USB port, and the data travels along the bus.

Discussion point: Investigate storage devices that can be connected to a PC through a USB port. For two of them, find out which USB technology they use and how fast they could transfer data. How does that compare with a hard drive inside the computer?

Specialised multimedia ports

VGA (Video Graphics Array): connects a second screen with a high-resolution display, but it carries no audio, so it is a poor choice for video.
HDMI (High Definition Multimedia Interface): carries high-quality video and its audio to a screen.

🎮 Which port?

🔁 5.06 The fetch–execute cycle Figure 5.03

Its full name is the fetch, decode and execute cycle.

Fetch

With a program already running, the PC already holds the address of the next instruction. Then:

The address in the PC is copied, inside the CPU, to the MAR.
In the next clock cycle, two things happen at the same time:
- the instruction at the address in the MAR is fetched into the MDR
- The address in the PC is incremented
The instruction in the MDR is copied, inside the CPU, to the CIR.

That clock cycle is the one set by the system clock, which allows exactly one transfer from memory per cycle.
The PC goes up by 1, but the new instruction might be a jump. Then the PC must be changed to match the jump condition, and that can only happen after decoding.

Decode

The instruction in the CIR is the input to the control unit's circuitry. Depending on the instruction, the control unit sends signals to the right components so execution can start; the ALU is switched on if arithmetic or logic is needed.

Execute

Execution depends on the instruction. Chapter 6 introduces a simple instruction set; the lab below previews three of its instructions.

✍️ 5.07 Register transfer notation (RTN)

RTN is a compact way to write what happens to registers. Here is the fetch stage:

MAR ← [PC]
PC ← [PC] + 1; MDR ← [[MAR]]
CIR ← [MDR]

Symbol	Meaning
MAR ← …	Like an assignment: the register on the left is the destination; the arrow shows data moving into it.
[PC]	Square brackets mean "the contents of" that register. The transfer may include arithmetic, such as [PC] + 1.
;	Two transfers on one line, separated by a semicolon, happen simultaneously.
[[MAR]]	The MAR contains an address; double brackets mean "the contents of the memory location at that address".

🔬 Lab: step through a program

A three-instruction program adds two numbers. LDD loads a value from memory into ACC, ADD adds one to it, STO stores ACC back to memory. Press Step to see each register transfer.

Ready.

Address bus: –Data bus: –

Address	Contents

🎮 Drill: after the fetch

PC MAR CIR

🎮 What does this RTN line mean?

🚨 5.08 Interrupt handling

An interrupt is a signal asking the processor to stop what it is doing and deal with something else. Some causes:

A fatal error in a program
A hardware fault
a need for I/O processing to begin
User interaction
A timer signal

Discussion point: Investigate the different causes of an interrupt.

Principles

Every type of interrupt needs its own handling, and different interrupts can have different priorities.
So the processor must be able to tell interrupts apart. One way is an interrupt register that works like the status register: each bit is a flag for one type of interrupt.
As Figure 5.03 shows, interrupts are checked only at the end of a fetch–execute cycle. The current program is therefore left in a defined state that can be returned to later.

Handling an interrupt

The PC and the other registers are saved somewhere safe in memory.
The start address of the right interrupt service routine (ISR), or interrupt handler, is loaded into the PC.
When the ISR finishes, the processor immediately checks for further interrupts.
Any further interrupts are handled by running the ISR process again.
When none are left, the saved register contents are restored, and the original program carries on.

🔬 Lab: the interrupt register

Raise one or more interrupts by setting their flags, then run fetch–execute cycles. Flags are checked only at the end of each cycle, and the highest priority (leftmost) is served first.

🎮 Put interrupt handling in order

Reflection point: Have you found a way to remember the names and short forms of all the special-purpose registers?

One idea

Follow the fetch in order: PC → MAR → MDR → CIR, "Please Make My Coffee". Then add the extras: ACC (the one general-purpose register), IX (indexing) and SR (flags).

📌 Summary

The von Neumann architecture is based on the stored program concept.
The CPU contains a control unit, an ALU and registers.
Registers are either special purpose or general purpose.
The status register has individual bits that act as condition flags.
The system bus is made up of the data, address and control buses.
A USB port can be used to attach peripheral devices.
Instructions are handled by the fetch–execute cycle.
Register transfer notation describes data transfers.
When an interrupt is detected, control passes to an interrupt-handling routine.

🃏 Key-term flashcards

Tap a card to flip it.

✅ Quick quiz

📝 Exam-style questions

Write your answer first, then open the model answer. These are my mark-scheme-style points, not official mark schemes.

The accumulator (ACC).

(i) It holds the address of the memory location (or I/O component) that is about to be read from or written to.
(ii) An address.
(iii) The program counter (PC).

(i) It holds the current instruction while it is decoded and executed.
(ii) An instruction (opcode and operand).
(iii) The memory data register (MDR).

The MAR holds an address; the MDR holds data, which may be an instruction, a value or an address.
The MAR is connected to the address bus, which is one-way (out of the CPU). The MDR is connected to the data bus, which is two-way.
The MAR is loaded from the PC (or from an instruction's address part). The MDR is loaded from memory, or from the accumulator before a write.
The MDR acts as a buffer between the fast processor and slower memory; the MAR only selects the location.

Address bus: carries an address from the MAR to memory or to an I/O controller, to select a location. It is one-way only.
Data bus: carries data, instructions or addresses between the CPU, memory and I/O devices, in both directions.
Control bus: carries control and timing signals to and from the control unit, so that transfers are synchronised by the clock.

(i) The number of wires, which is the number of bits sent at once (in parallel). It is chosen to suit the word length.

(ii) The control bus. It carries only control and timing signals, never word-sized values, so about 8 lines are enough.

(iii) The number of directly addressable locations rises from 2³² (about 4 billion) to 2⁶⁴, so much more memory can be addressed directly, without slower special techniques. The MAR and other address-handling parts must become 64 bits wide, and the bus needs twice as many lines.

(a)

Definitions: MAR, the memory address register, holds the address to be read or written. PC, the program counter, holds the address of the next instruction. MDR, the memory data register, holds data read from or going to memory. CIR, the current instruction register, holds the instruction being decoded and executed. [ ] means "the contents of"; ← means "is transferred to"; ; means at the same time; [[MAR]] means the contents of the memory location whose address is in the MAR.
MAR ← [PC]: the address of the next instruction is copied from the PC to the MAR.
PC ← [PC] + 1; MDR ← [[MAR]]: at the same moment, the PC is incremented to point to the following instruction, and the instruction stored at the address in the MAR is copied into the MDR.
CIR ← [MDR]: the instruction is copied from the MDR into the CIR, ready to be decoded.

(b) In MDR ← [[MAR]], the address in the MAR is put on the address bus to select the memory location, and the instruction stored there comes back on the data bus into the MDR. The other two statements are transfers inside the CPU, so they do not use the system bus.

The same three as 2a: the address bus (one-way, carries addresses from the MAR to memory or I/O), the data bus (two-way, carries data, instructions or addresses) and the control bus (two-way, carries control and timing signals).

(i) The program counter is incremented by 1, so it holds the address of the next instruction.
(ii) The contents of the memory location whose address is in the MAR are copied into the MDR.
(iii) The contents of the MDR (the instruction) are copied into the CIR.

The address 35 (from the instruction in the CIR) is placed in the MAR. The contents of memory location 35 are copied into the MDR, then into the accumulator. In RTN: MAR ← 35; MDR ← [[MAR]]; ACC ← [MDR].

(i) A signal from a device or program (or a hardware fault, or a timer) asking the processor for attention. It makes the processor suspend the current program for a while.

(ii)

The interrupt is detected at the end of the current fetch–execute cycle.
The interrupt register identifies the type and priority of the interrupt.
The PC and other registers are saved to memory.
The start address of the ISR is loaded into the PC, and the ISR runs.
The processor checks for further interrupts. If there are none, it restores the registers and resumes the original program.

Cambridge International AS & A Level Computer Science 9608, Paper 13 Q5, June 2015

The PC holds the address of the next instruction, which is copied to the MAR.
The PC is then incremented.
The instruction at the address in the MAR is copied, via the data bus, into the MDR.
The instruction is copied from the MDR into the CIR.

At the end of the cycle for the current instruction, B (the processor checks if there is an interrupt).
If the interrupt flag is set, D (the register contents are saved), A (the address of the ISR is loaded to the PC) and C (when the ISR completes, the processor restores the register contents).
The interrupted program continues its execution.

Cambridge International AS & A Level Computer Science 9608, Paper 11 Q3, June 2016

Guru Jazzy · Cambridge AS & A Level Computer Science · Chapter 5 Processor Fundamentals · Figures from the Cambridge coursebook (Langfield & Duddell)